Buffer



d. 17, 1967 F, E, BROOKS 3,348,209

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IMAO( (haw/ Mr/MV 3 Sheets-$heet 5 F. E. BROOKS BUFFER Oct. 17, 1967Filed Nov. 27, 1964 United States Patent O 3,348,209 BUFFER Forrest E.Brooks, Moorestown, NJ., assignor to Radio Corporation of America, acorporation of Delaware Filed Nov. 27, 1964, Ser. No. 414,194 Claims.(Cl. S40-172.5)

ABSTRACT OF THE DISCLOSURE A buffer and buffer control system isprovided which includes a data storage means and means for transferringdata between a data handling device, for example, a computer, and aninput-output device through the storage means. The buffer is operable ina transmit mode which data is transferred in one direction between thedata handling device and the input-output device, in a receive mode inwhich data is transferred in the opposite direction between the datahandling device and the input-output device or in a neutral mode inwhich no data transfer takes place, in response to control signalsderived from the presence or absence of data at the data handlingdevice, the input-output device, and the buffer. Since the neutral modealways exists before and after a data transfer in either directionbetween the data handling device and input-output device, consecutivetransfers in one direction between the data handling device and theinput-output device are possible without an intervening transfer of datain the opposite direction.

This invention relates to buffers and buffer controls, and particularlyto an improved buffer and buffer control for controlling the transfer ofdigital data between a data handling device, for example, a computer,and an inputoutput device.

The transfer of data between a computer and an inputoutput device, suchas a teleprinter, by way of a telegraph, telephone or other transmissionline generally requires that a buffer be placed 'between thetransmission line and the computer memory which receives and stores thedata information. The buffer is necessary in order to compensate fordifferent rates of data occurance, data generally occurring over atelegraph or telephone transmission line at a slower rate than that ofdata within a computer, and in order to provide storage between thetransmission line and the computer so that the computer memory need notbe directly connected to the line at all times.

Buffers and buffer controls which allow data transfer both to thecomputer from an input-output device via a transmission line and fromthe computer to the input- Output device via the same transmission linehave in the past generally required that the data be transferredalternately between computer and the input-output device. That is, atransfer of a completed data message from the input-output device to thecomputer must be followed by a transfer of a completed data message fromthe cornputer to the input-output device before a following data messagecan be transferred from the input-output device to the computer, andvice versa.

It is an object of the present invention to provide an improved bufferand buffer control.

It is a further object of the present invention to provide an improvedbuffer and buffer control which enables data transfers both to and froma computer and which allows any number of completed data transfers tooccur one after the other in the same direction.

3,348,209 Patented Oct. 17, 1967 The present invention may be brieflydescribed as a butter which has three modes of operation. The threemodes will be called, (l) the transmit mode, where the transfer of datais from the computer to an input-output device via a transmission line,(2) the receive mode, where the transfer of data is from theinput-output device to the computer via the transmission line, and (3)the neutral mode where no data is being transferred. As long as no datais being transferred, the buffer remains in the neutral mode. When thecomputer is ready to transfer data to the input-output device via thetransmission line, the buffer shifts from the neutral mode to thetransmit mode. Conversely, if data is received over the transmissionline from the input-output device, the buffer shifts from the neutralmode to the receive mode. Once the buffer is shifted to either thetransmit or receive mode, it remains in that mode until the data istransferred to and from the buffer. When the transfer is completed, thebuffer shifts back to the neutral mode. By providing the neutral modefor the condition of no data being transferred, the buffer is capable ofshifting to either the transmit or receive mode from the neutral mode inan unrestricted manner to transfer data in either direction .between thecomputer and the input-output device. This is in contrast to previouslyknown buffers in which only a transmit and a receive mode are provided.In the latter case, since the Abuffer upon completing the transfer ofdata in one mode shifts to the second mode, only two modes beingprovided, the buffer must complete a transfer of data in the second modebefore it can complete a further transfer of data in the first mode.This restriction on the operation limits the versatility and applicationof the buffer.

A more detailed description of one embodiment of the present inventionwill be given with reference to the accompanying drawing in which:

FIG. 1 is a block diagram of the buffer and buffer control of oneembodiment of the present invention.

FIGS. 2-ll are logic diagrams useful in describing a typicalconstruction and operation of the buffer control as shown in theembodiment of FIG .1.

In describing the invention, reference will be made to the terms ONE andZERO. These terms are to be understood in the usual manner where ONEsignifies a first of two possible binary signal levels and ZEROsignifies the second, different binary signal level. The terms areapplied in the manner accepted in the art.

In the block diagram of FIG. 1 a transmission line 1 provides a path forthe transfer of data in either direction between an input-output device2 here illustrated as a teleprinter and a register 5 of a computer. Thetransmission line 1 is coupled to a buffer register 4 through an inputdata control unit 3. The buffer register 4 is a conventional shiftregister including by way of example a sequence of flip-Hops as storageelements and is capable of storing one character of telegraph datawhich, as will be explained more fuliy below, includes by way of exampleVseven bits of variable information, a slop bit and a start bit. Thus,the hulfer register 2 contains nine storage elements. The last storageelement of the buffer register 4 contains the character' start bit whena complete character is contained in the register. This storage elementwill be referred to as the start lip-op. Similarly, the first storageelement of the butler register 4 contains the character stop bit andwill he called the stop Hip-flop. A line rela 6 is inserted in thetransmission line 1 to control the conduction of the transmission line 1in response to data signals applied to the line relay 6 in theconventional manner in order to transmit data to the teleprinter 2 viathe transmission line 1. While a line relay is shown it will be evidentto one skilled in the art that other suitable means may be employed tocontrol the conduction of the line 1. The buffer register 4 is connectedfor a parallel transfer of data to or from the computer register 5through a plurality of transfer gates 7. Neither the stop nor start bitof a data character is transferred to the computer register 5, and ittherefore contains only seven storage elements. While the specificconstruction details of the computer register 5 depend on the particularcomputer employed, the register 5 must allow for parallel transfer ofinformation to and from the buffer register 4.

Output data is fed from the buffer register 4 to the transmission line 1by way of the output data control circuit 8 and the line relay 6 whichcontrols the state of conduction of the telegraph line 1. The operationof the buffer is controlled by the buffer mode control unit 9. The modecontrol unit 9 receives input signals from the line 1 and interfacecontrol unit 1t). It sends control signals to the input data control 3,the output data control 8, the transfer gates '7, a counter unit 11which controls the shifting of the buffer register 4, an error detectingcircuit l2, and the interface control unit I0. The counter unit 11includes a conventional counter which is used to advance the buffershift register 4 at the line data bit rate. The interface control unitestablishes communication between the mode control unit 9 and acommunication mode control (CMC) 13. Detailed description of logiccircuitry usable within the various blocks of FIG. 1 is given by way ofexample in the remaining FIGS. 2-l0.

Before describing the operation of the buffer and mode control of thepresent embodiment, the signals which act to control the mode controllogic and butter operation will be described.

A computer which is equipped to handle digital data informationgenerally includes a control unit which, in FIG. l, is designated as thecommunication mode control (CMC) unit 13. Such control units are wellknown and are not per se the subject of the present invention. However,a brief description of the operation of the CMC used with the presentembodiment will be given.

Generally, a plurality of transmission lines and their respectivebuffers are associated with any one computer. The CMC unit 13 isprovided to determine which of the buffers will operate with thecomputer at any one time. In order to control the buffer selection, twobinary signals are generated by the CMC13 and sent to the interfaceunits of the various buffers associated with the computer. In the bufferof FIG. l, the two signals are sent from the CMC13 to the interface 1i).The first of these signals, which will be called Select (Sel), performsan interrogating function with respect to the buffer. When Sel is in onecurrent condition defined as ONE, for example, the buffer isinterrogated to determine whether the buffer is ready to either receivea data character from the cornputer or transfer a data character to thecomputer. If the buffer is ready, then, the Sel signal remains in theONE condition until the transfer to or from the computer has beencompleted. The second signal, which will be called Computer Ready (CR),is sent by the CMC13 to a buffer to indicate to the buffer whether thecomputer is ready to transfer or receive a character. If the computer isready, CR is in the ONE condition; if the computer is not ready, CR isin a second current condition defined as ZERO, for example.

In addition to the two above-mentioned signals, Select and ComputerReady, the present embodiment utilizes certain characteristics oftelcgraphic data. The smallest unit of telegraph data is a bit which maybe a binary ZERO (no current on the telegraph line) or a binary ONE(current on the telegraph line). A character, the next larger data unit,comprises a plurality of bits. A word comprises a plurality ofcharacters, and a message a plurality of words. Each character of datasent in either direction over the line 1 contains a start bit which isalways a ZERO and a stop bit which is always a ONE. The bits in betweenthe start and stop bits are variable and constitute the actual digitalinformation contained within the character. The characters used with thepresent embodiment contain seven bits which are variable and constitutethe digital information. These seven bits are spaced between a start bitwhich is always a binary ZERO and a stop bit which is always a binaryONE. The stop bit is actually three bit times long, i.e. it is threetimes as long as any of the other bits. Thus, with a three bit time stopbit and a one bit time start bit the total character length is elevenbit times.

The three bit time stop bit is used in the present embodiment to providesufficient time for the seven information bits contained in a characterto be shifted from the buffer register 4 to the computer register S andto be processed by the computer before the next character enters thebuffer register 4 from the line 1. Thus, when the buffer is receiving amessage from the line 1, the first nine bits of a character are shiftedinto the buffer register 4. During the last three bit times, thecharacter is stationary in the buffer registry. During this time theseven information bits are transferred to the computer memory by way ofthe computer register 5. After these three bit times, the next characteris shifted into the buffer register 4 and the process is repeated.

If it is desired to use some other character construction which does notcontain a stop bit or contains a stop bit of insufficient length, asecond register may be provided between the buffer register 4 and thecomputer register 5. Such a modification will be evident to one skilledin the art.

As noted above, Sel is sent from the CMC13 to interrogate the buffer asto its present state, i.e. to determine whether the buffer is ready totransfer or receive data to or from the computer. The state of thebuffer is indicated by two binary signals established at the interface10 and sent to the CMC13. The first binary signal which will be calledBuffer Ready (BR) indicates Whether the buffer is ready. If the bufferis ready, BR is in the ONE condition; if not ready, BR is in the ZEROcondition. The second binary signal called Buffer Direction (BD)indicates the direction of the transfer for which the buffer is ready.If the buffer is ready to transfer data to the computer, then BD isZERO; if the buffer is ready to receive data from the computer, then BDis ONE. When the select signal Sel sent by the CMC13 is a ONE, then, aninterrogating pulse is developed at the interface 10 and the interface10 indicates the present state of the buffer by sending the BR and BDsignals. If the buffer is ready, BR is in the ONE condition, then Selremains at the ONE level; if the buffer is not ready, Sel goes to ZEROand remains there until the CMC13 is again ready to interrogate thebuffer. Assuming the buffer is ready, BR is ONE, then if the buffer hasa character for the computer, BD is ZERO, the CMC13 will cause CR to beONE when the computer is ready to receive the character. It, on theother hand, the buffer is ready to receive a character from thecomputer, BD is ONE, then the CMC13 will cause CR to be ONE when thecomputer is ready to transfer a character to the buffer.

In addition to Buffer Ready, BR, and Buffer Direction, BD, the interface10 also sends a third signal which will be called Error (ERR) toindicate whether there has been an error in the transfer of information.The error signal and the computer response to it will be described inmore detail below.

The mode control 9 controls the operation of the buffer by determiningits mode of operation. When there is no data either entering or leavingthe buffer, the mode control 9 will establish the neutral mode. In theneutral mode the following functions are performed:

(1l The transfer gates 7 between the buffer register 4 and the computerregister 5 are rendered operative to the transfer of data to the bufferregister 4 from the computer register S. That is, as soon as CR from theCMC13 is ONE indicating a ready state in the computer a character in thecomputer register S will be transferred to the buffer register 4.

(2) The input data control 3 is rendered operative to the transfer ofinformation from the telegraph line 1 to the buffer register 4.

(3) The counter 11 which controls the shifting of the buffer register 4is inoperative, and the buffer register 4 receives no shifting pulses.

(4) `Upon interrogation, the signals BR and BD at the interface willboth be ONE, indicating that the buffer is ready to receive informationfrom the computer.

(5) No error indication is present in the error detecting circuitry 12,and the error signal ERR is ZERO.

A shift from the neutral mode to the transmit mode occurs when the CMC13indicates to the interface 10 that the computer is ready to send amessage to the buffer, i.e. CR is ONE. The CMC13 iuterrogates the bufferby sending Sel. If the buffer is in the neutral mode, it is ready toreceive a character from the computer. When the computer is ready tosend a character, CR becomes ONE. The ONE condition of Sel and CR shiftsthe buffer to transmit. When the buffer shifts to transmit, thefollowing functions are performed:

(1) The CR signal enables the transfer gates 7 for the transfer of acharacter from the computer register 5 to the buffer register 4.

(2) The counter 11 is rendered operative.

(3) Buffer register advancing pulses from the counter 11 are applied tothe buffer register 4.

(4) The output data control 8 is rendered operative, and the characterwhich has been transferred to the buffer register 4 from the computerregister 5 is shifted out of the buifer register 4 and is transferred tothe transmission line 1 via the line relay 6.

(5) Errors which might be present are detected.

(6) The interface unit 10 indicates a not ready condition (BR is ZERO),to the CMC13.

(7) When the character has been completely shifted to the line 1, theinterface 10 again indicates a ready condition, the next character ofthe message is sent from the computer register 5 to the buffer register4, and the process is repeated.

After the message has been transferred to the telegraph line 1, the modecontrol 9 detects the presence of no data on the line 1 and the buffershifts back to its neutral mode. A shift from the neutral to the receivemode occurs as soon as any information appears on the telegraph line 1.In the receive mode the following functions are performed:

(1) The input data control 3 is rendered operative and the data on thetelegraph line 1 is applied to the input of the buffer register 4.

(2) The counter 11 is rendered operative.

(3) The advancing pulses from the counter 11 are applied to the bufferregister 4, and the rst nine bits of the character are shifted into thebuffer register 4.

(4) Errors which may be present are detected.

(5) While the character is being shifted into the buifer register 4, theinterface unit 10 indicates a not ready state (BR is ZERO), to theCMC13.

(6) When the rst nine bits are received, the interface 10 indicates aready state, and when the computer is ready to receive the character, CRbecomes ONE.

(7) The transfer gates 7 are rendered operative, by the CR signal, forthe transfer of data from the buffer register 4 to the computer register5 and the seven information bits are transferred to the computerregister 5.

(8) The CR signal sets a not ready state (BR is ZERO), at the interface10, the next character is transferred to the buffer register 4, and theprocess is repeated.

After a complete message has been transferred from the CTI line 1 to thecomputer, the buffer shifts back to the neutral mode.

FIG. 2 is a logic diagram of the basic circuitry contained within themode control 9 shown in FIG. 1. This circuitry includes two ip-ops 30and 31, labeled respectively TR-RC and N-, the states of which determinethe particular mode of operation of the buffer, i.e. transmit, receiveor neutral. These two flip-Hops 30 and 31 are the conventional set-resettype, that is when a binary ONE is applied to the S (set) terminal ofthe flip flop then the iiip flop will set and a ONE will appear at theoutput terminal designated 1 in the diagram. When a ONE is applied tothe R (reset) terminal, the tiip tiop will reset and a ONE will appearat the output terminal designated O in the diagram.

The two signals sent by the CMC13, Sel and CR provide two inputs to anAnd gate 33, the output of which is supplied to the input of an And gate3.2. The second input to the And gate 32 is taken from the outputterminal 1 of the N- flip-flop 31. The output of the And gate 32 isapplied to the set terminal S of the TR-RC Hip-flop 30. The output ofthe And gate 33 forms the output signal SelCR. (The Boolean function andwill be expressed as a dot in this description and the Boolean functionor as a plus sign l-.) The data on the transmission line 1 (LINE DATA)is directed to an And gate 52 and to a conventional one-shotmultivibrator 51, the output of which is supplied to the And gate 52.The following notation will be used to describe the operation of theone-shot 51 and all the other one-shots used in the various logicdiagrams. The binary number at the input of the one-shot, a ZERO in thecase of the one-shot 51, represents the state to which the input must beshifted in order to produce the designated output. The binary number atthe output of the one-shot, a ZERO in the case of oneshot 51, representsthe binary output of the one-shot when the designated input is applied.Thus, when the input to the one-shot 51 changes from a ONE to ZERO, theoutput will also change from a ONE to a ZERO and will remain a ZERO fora predetermined length of time. As will be explained in detail below,the output of the oneshot 51 remains a ZERO for slightly more than onecharacter time after the input to the one-shot 51 shifts from a ONE to aZERO.

The output of the And gate 52 is supplied to a oneshot .35. The one-shot3S develops a short ONE pulse when its input shifts to ONE. The outputof the oneshot 35 forms the signal Neutral Set (NS) which is applied tothe reset terminal R of the TR-RC Hip-flop 30 and the set terminal S ofthe N- lip-flop 31. LINE DATA is also supplied through an inverter 39 t0one input of an And gate 44 which also receives the condition at theoutput terminal O of the TR-RC flip flop 30. The output of the And gate44 is fed through an Or gate 41 to an And gate 36 as is the output ofthe And gate 32. A second input to the And gate 36 is taken from theoutput of a one shot 40 which receives the Sel signal as an input.Following the one-shot notation described above, when the input to theone-shot 40 changes from ZERO to ONE, then the output of the one-shot 40changes from ONE to ZERO` The ZERO output remains for a short period oftime as will be explained below. The output of the And gate 36 isapplied to the reset terminal R of the N- flip-flop 31. The output fromterminal O of the N- ip-op 31 is labeled and the output from theterminal 1 is labeled N. The condition at the output terminal 1 of theN- flip-ilop 31 is supplied to the input of a one-shot 50, the output ofwhich forms the Neutral Reset (NR) signal. The outputs of the TR-RCflip-flop 30 are labeled TR and RC.

The operation of the logic of FIG. 2 may best be demonstrated by firstconsidering the various output signals and their functions. As notedabove the outputs of the two ilip-tiops 30 and 31 determine the mode ofoperation of the buffer. In the transmit mode, TR is ONE and is 7 ONE.In the receive mode RC is ONE, and is ONE. In the neutral mode RC isONE, and N is ONE. The two output signals NS and NR are used to performvarious functions when the buffer is shifting to or from the neutralmode.

When the buffer is in the neutral mode i.e. the TR-RC flip-flop is resetand the N- flip-flop is set, the buffer may be shifted to one of itsother modes by the input signals. If the select and computer readysignal (Sel-CR) appears at the input of the And gate 32 indicating thatthe computer is ready to send a character to the buffer, then the outputof the And gate 32 will be ONE, N being a ONE, and the TR-RC flip-flop30 will set causing TR to become ONE. Also, the output of the And gate32 appears at the input of the And gate 36 via the Or gate 41 and resetsthe N- ilip-op 31 placing the mode control in transmit.

The output of the one-shot 40 will be a ONE shortly after the selectsignal appears at the input. That is, when Sel is a ONE, the output ofthe one-shot 40 will go to ZERO for much less than a bit time and thenreturn to ONE. The one-shot 4t] is included to insure that the modecontrol will not shift from neutral while the buffer is beinginterrogated. As pointed out above, Sel is sent by the CMC13 tointerrogate the buffer as to its present condition as indicated by theBR, BD and ERR signals developed at the interface 10. In order toprevent the buffer from changing its mode while being interrogated theoneshot 40 generates an inhibiting pulse, ZERO, while the butter isbeing interrogated. The flip-flop 31 is held nonresponsive to thecondition otherwise passed by the And gate 36 from the output of the Orgate 41. The ZERO pulse developed by the one-shot 40 when its input goesto ONE is equal in length to that of the interrogating pulse developedat the interface 1l). After interrogation the output of the one-shot 4Ggoes back to ONE, making the flip-flop 31 again responsive to the outputof the Or gate 41 and permitting the buffer to be shifted to thetransmit mode.

The neutral to receive shift occurs when data appears on thetransmission line 1. When data appears on the transmission line l, thestart bit of the data character causes a ONE to ZERO transition of thetransmission line 1. The ONE to ZERO transition establishes a ONE at theoutput of the inverter 39 and at the input to the And gate 44. Thesecond input to the And gate 44, RC, is a ONE because the buffer is inthe neutral mode. The resulting ONE output of the And gate 44 resets theN- flip-flop 31 through the Or gate 41 and the And gate 36 causing thesignal to become a ONE thus placing the buffer in receive. Again, theone-shot 40 prevents the resetting of the N- ilip-op 31 duringinterrogation.

The shift from either transmit or receive to neutral is accomplished bygap detector logic which includes the one-shot 51, the And gate 52, andthe one-shot 35. The gap detector, which is of conventional design,detects the transition from data to no data on the transmission line l.The output of the one-shot 51 is a ZERO for slightly more than onecharacter time after a ZERO appears at its input. As long as data iseither being transmitted or received over the transmission line 1, thecharacter start bits, ZEROS will keep the output of the one-shot 51 atZERO. When no data, i.e. a continuous ONE, appears on the transmissionline 1, the output of the one-shot 51 will become ONE. Both inputs ofthe And gate 52 will then be ONE and the NS signal at the output ofoneshot 35 will go to ONE. This NS signal resets the TR-RC flipflop 30and sets the N- flip-flop 31, thus placing the buffer in the neutralmode. Methods other than gap detection may of course be used to causethe shift to neutral. For example, in some cases it may be desirable totrans mit an end of message signal along with the message to cause theshift to neutral.

FIG. 3 is a diagram of the logic used to control the operation of thecomputer-to-buffer transfer gates i.e. the gates included within theblock 7 of FIG. 1, which control the information transfer from thecomputer to the buffer. Each transfer gate is a two input And gate whichhas one input connected to one memory element or flipflop of thecomputer register 5. The output of each gate is connected to arespective memory element of the buffer register 4. The second input ofeach And gate is the control input and is connected to the output of Andgate 62 of FIG. 3. The FIG. 3 logic, which is included in the modecontrol 9 of FIG. l, consists of a two input Or gate 60 which receivesthe TR and the N signals from the logic of FIG. 2. The output of the Orgate 60 is connected to one input of an And gate 62. The Sel CR signalfrom the FIG. 2 logic is applied to a second input of the And gate 62.

When the output of the And gate 62 is a ONE, then the computer-to-butertransfer gates are enabled and a character in the computer register 5 istransferred to the buffer register 4. As pointed out above, data may betransferred from the computer register 5 to the buffer register 4 ineither the transmit or neutral mode. When the buffer is in either ofthese two modes, the output of the Or gate 60 will be ONE, and thecomputer to buffer transfer gates will be enabled as soon as Sel'CR issent from the CMC.

FIG. 4 is a diagram of the logic, included in the mode control 9 of FIG,1, which is used to control both the buffer-to-computer transfer gatesincluded in the block 7 of FIG. 1. and the setting of the bufferregister 4. The buffer-to-computer transfer gates are the same as thecomputer-to-buffer transfer gates except for the direction of transfer.The logic used to control the buffer-t0- computer transfer gatescomprises a three input And gate 65 where the three inputs are SelCR,RC, and N. These three signals are taken from the logic of FIG. 2. Theoutput of the And gate 65 is supplied to the control terminal of each ofthe butfer-to-computer And gates. Thus, information is transferred fromthe buffer register 4 to the computer register 5 when the output of theAnd gate 65 is a ONE. This occurs when the mode control is in thereceive state i.e. RC and N are both ONE, and Sel-CR is ONE.

The buffer register 4 in FIG. 1 includes a set line which permits theregister to be cleared of all data when a ONE is applied to the setline. The set line is connected to the output of the one-shot 69 in FIG.4. Thus when the oneshot 69 output goes to ONE, the buffer register 4 isset. The input to the one-shot 69 is taken from the output of the Andgate 66. The two inputs to the And gate 66 are NS and the output of theinverter 617 which is connected to the output of the And gate 65.

The inverter 67, the And gate 66 and the one-shot 69 act to set thebuffer register 4 when the buffer shifts to neutral from receive. Thatis, when the last character of a message has been received from the line1 by the butTer register 4 and has been transferred to the computerregister 5, the SelCR signal to the And gate 65 goes to ZERO causing theoutput of the And gate 65 to go to ZERO and the output of the inverter67 to go to ONE. Since there is no more data on the line 1, the NSsignal will be ONE and the one-shot 69 is triggered. The output of theone-shot 69 then sets the buffer register 4.

FIG. 5 is a diagram of the logic used to control the line relay 6 ofFIG. 1 by which a character in the buffer register 4 is transmitted tothe line 1. This circuit corresponds to the output data control 8 inFIG. 1. The logic comprises a two input Or gate 71 which receives the TRand N signals from the logic of FIG. 2. The output of the Or gate 71 isapplied to an And gate 70, the output of which is connected through aninverter 72 to the line relay 6. The second input to the And gate 70 isthe output of the start flip-flop in the buffer register 4. The startflip-flop is the last flip-flop in the buffer register 4. When there isa complete character in the buffer register 4, i.e. a ZERO start bit inthe start ip-0p, then the output of the start flip-flop, which is calledSTART, is a ONE. As data is shifted from the buffer register 4, thestart Hip-flop applies the data to the And gate 70. The TR and N signalsapplied through the Or gate 71 to the And gate 70 enable the transfer ofdata from the butter register 4 to the line relay 6 when the buffer isin the transmit or neutral mode and the butter register 4 contains acharacter.

FIG. 6 is a logic diagram of the input data control unit 3 of FIG. 1.The logic comprises an And gate 74 which receives the input data fromthe line (LINE DATA) and the RC signal from the FIG. 2 logic. The outputof the And gate 74 is applied to the irst flip-iiop of the butterregister 4 i.e. the stop llip-iiop. Data will be applied to the stopiiip-op in either the neutral or receive modes since RC is a ONE ineither of these modes.

FIG. 7 is a diagram of the logic used to control the counter included inthe block 11 of FIG. 1, which controls the shifting of the bufferregister 4. The counter itself may be of conventional construction. Asuitable counter for the present embodiment comprises a plurality ofset-trigger-reset Hip-Hops driven by an oscillator. The output of one ofthe counter flip-hops is used to provide shifting pulses for the buiierregister 4. The bit rate of this flip`op should be twice the bit rate ofdata on the line 1 so that positive pulses will be applied to the butterregister 4 at the data bit rate. The counter unit 11 also provides anindication of a complete character transfer to or from the butterregister 4. Suitable logic of conventional design is employed to providea signal which Will be a ONE when the counter has counted to eleven.This signal will be called, character tirne (CT).

In the FIG. 7 logic, inverted data from the transmission line 1 (DATA)and the RC signal from the FIG. 2 logic are applied to an And gate 75the output of which is connected to the reset terminal R of a set-resetflip-ilop 76. The outputs of the start and stop tiipflops of the butterregister 4 and the output (OSC) of the oscillator which is used to drivethe counter of the counter unit 11 are supplied to an And gate 77. Theoutput of the And gate 77 is connected through an Or gate 78 to the setterminals of the dip-flop 76. The neutral shift signal, NS, from theFIG. 2 logic, is applied to a second input of the Or gate 78. The outputat terminal 1 of the iiip-ilop 76 is applied to an And gate 79 whichalso receives the RC signal from the TR-RC fiip-flop 30 in FIG. 2. Theoutput of the And gate 79, labeled A, is used in conjunction with otherlogic to be subsequently described. The output of the And gate 79 isapplied to one input of an Or gate 80 which also receives an input froman And gate 81. The two inputs to the And gate 81 are the TR signal andthe Sel-CR signal from the logic of FIG. 2. The output of the Or gate 80is applied to the reset terminal R of each of the set-trigger-resetHip-Hops contained within the counter. Thus, when the output of the Orgate 80 is a ONE, all of the counter flip-flops are held in the resetstate and the counter will not count.

As noted above, the counter counts only when a character is beingtransferred either from the line 1 to the butter register 4 or from thebuffer register 4 to the line l. The FIG. 7 logic holds the counter inreset thus preventing it from counting when the butter register 4 isneither transferring to nor receiving from the transmission line 1. TheSelCR and TR signals applied to the And gate 81 will cause the counterflip-Hops to be held in the reset position while a character is beingtransferred from the computer register to the buffer register 4. Afterthe character has been transferred to the buffer register 4, the Sel-CRsignal goes to ZERO and the counter is released. The RC signal and theONE output of the ilip-op 76 are applied to the And gate 79 to ensurethat after a character has been transferred to the buffer resistor 4from the line 1, the counter 10 will stop counting. The flip-flop 76 isused to detect the presence of a character in the butler register 4during the receive mode. When a character has been received the outputat the terminal 1 of the flip-flop 76 and the A signal will both be ONE.When a character has been received in the buffer register 4, the startbit of the character will cause the output of the start flip-liep(START) to be a ONE and the stop bit of the character will cause theoutput of the stop flipop (STOP) to be a ONE. START and STOP cause theoutput of the And gate 77 to set the liip-tlop 76 through the Or gate 78when a character has been received in the butter register 4. Setting theiiip-tlop 76 will then stop the counter. The OSC input to the And gate77 is used as a timing pulse to synchronize the setting of tlipntlop 76with the counter operation. When the start bit of the next character isreceived, the Hip-flop 76 will reset due to the ONE output of the Andgate and the process will be repeated. When the complete message hasbeen trans fcrred to the computer' and the mode control shifts toneutral, the counter will remain olf due to the setting of the iptiop 76by the neutral shift, NS, signal applied to the Or gate 78.

The application of the counter output pulses to the buffer register 4 iscontrolled through the logic of FIG. 8 which is contained within theunit 11 in FIG. l. The output of one of the counter ipJiops, P, isapplied to the input of an And gate 86 which also receives the TRsignal. The pulse rate of P is twice that of the telegraph character bitrate. With P repeating at twice the bit rate, positive pulses whichadvance the buffer register 2 are repeated at the bit rate. The P pulsesare also applied, through the inverter 87, to the And gate whichreceives the RC signal.

When the butter is transferring a character from the butler register 4to the transmission line 1, TR is ONE and advance pulses are applied tothe butter register advance line through the And gate 86 and the Or gate88. When the butler register 4 is receiving a character' from thetransmission line 1, RC is ONE and advance pulses are applied to thebuier register advance line through the inverter 87, the And gate 85 andthe Or gate 88. F, the output of the inverter 87, is used to advance theregister in the receive state rather than P in order that the incomingbit will `be transferred to the tirst flip-op of the butter register 4at the center of the bit. The P advance pulses go positive at thebeginning af a character bit time and therefore since the P pulse rateis twice the data bit rate the F advance pulses go positive at thecenter of the bit.

FIG. 9 is a logic diagram of the circuitry in the interface unit 10which produces the BR and BD signals. This logic includes two set-resetip-ops and 101 labeled respectively BR1 and BR2. An And gate 105receives the TR signal from the FIG. 2 logic and the character timesignal, CT, which is generated by the counter logic when the counter hascounted one character time, i.e. eleven. The output of the And gate 10Sis directed through an Or gate 106 to the input of a one-shot 107. Asecond input to the Or gate 106 is the A signal developed by the FIG. 8logic. The output of the one-shot 107 is applied to the input of an Orgate 108. Two other inputs to the Or gate 108 are the neutral set, NS,signal from the FIG. 2 logic and an error signal ER developed by thelogic of FIG. 1l to be subsequently described. The output of the Or gate108 is supplied to the set input terminal S of the BRI Hip-Hop 100. TheSel signal from the CMC13 is applied to a one-shot 110 and through aninverter 111 to the input of an And gate 112. The output of the one-shot110 is applied through an inverter 114 to a second input 0f the And gate112. A third input to the And gate 112 is taken from the output terminal1 of the BRI lip-op 100. The output of the And gate 112 is supplied tothe set input terminal S of the BRE flip-flop. The reset inputs of boththe BRI tlip-iiop 100 and the BRZ flip-[iop 101 are taken from theoutput of an Or gate 102 which receives the Sel-CR and NR signals fromthe logic of FIG. 2. The output at the terminal 1 of the BRZ ilip-iiop101 is supplied to an And gate 115 with the output of the one-shot 110and a no error signal, NER, developed by the logic of FIG. 11.. AnotherAnd gate 116 receives the TR-l-N signal which may be taken from theoutput of the Or gate 60 in FIG. 3, and the output of the one-shot 110.The output signals developed by the FIG. 9 logic are, F from the outputof the one-shot 107, D from the output terminal O of the BR1 flip-flop100, BD from the output of the one-shot 110- and BR from the output ofthe And gate 115.

The logic of FIG. 9 generates the two signals BR and BD which asexplained above, indicate the state of the buffer to the CMC14. The BRsignal is taken from the output of the And gate 115, and the BD signalfrom the output of the And gate 116. Both of these gates receive theoutput of the one-shot 110 and therefore the output of neither And gate115 nor And gate 116 can be a ONE unless the output of the one-shot 110is a ONE. The oneshot 110 output is applied to the two And gates 115 and116 as an interrogating pulse. When Sel from the CMC is a ONE at theinput of the one-shot 110, the one-shot 110 develops the interrogatingpulse at its output. When the interrogating pulse is present, the outputBD of the And gate 116 will be a ONE if the buffer is in either transmitor neutral mode (TR+N=ONE), and the output BD will be a ZERO if thebuffer is in receive (TR-t-N: ZERO). The BR signal from the output ofthe And gate 115, upon interrogation, will be a ONE when the BR2 ilip-opis set and there is no error indication (NER-.- ONE).

The state of the BRZ flip-flop 101, and therefore the BR signal, iscontrolled by the associated logic. When the buffer is in neutral theBRZ Hip-flop will be set, allowing the BR signal to indicate a readycondition, (BR is ZERO), upon interrogation. The change from ready (BRis ONE), to not ready (BR is ZERO), is accomplished by resetting the BRZflip-flop 101 through the Or gate 102. Thus, the BR; flip-flop 101 isreset when the NR signal from the FIG. 2 logic is generated indicating ashift from neutral to either transmit or receive. Consider rst the shiftfrom neutral to receive. Upon shifting from neutral to receive, the NRsignal is generated at the output of the one-shot 50 in FIG. 2, and theBRZ flip-hop 101 is reset through the Or gate 102. Upon interrogationthe BR signal will indicate not ready (BR is ZERO) and the bufferdirection BD, signal will indicate the receive state (BD is ZERO). Whilethe buffer is in the receive state, a character on the line 1 will betransferred to the butter register 4. When the character is completelytransferred to the register 4, the BRZ flipflop 101 will set and thesignals sent to the CMC13 will indicate that the buffer is ready totransfer a character to the computer (BR is ONE and BD is ZERO).

The setting of the BR2 Hip-flop 101 when the character has beencompletely transferred to the buffer register 4 is accomplished via theAnd gate 112 and the output at terminal 1 of the BR, ip-ilop 100. Whilethe character is being shifted into the buffer register 4, the BR1flipop 100 is in the reset condition due to the NR pulse applied to itsreset terminal when the buHer shifted to receive. Once the character hasbeen completely shifted into the buffer register 4, the BRl ip-op 100will beco-me set due to the presence of the A input to the Or gate 106.The A signal is taken from the logic of FIG. 7 and, as pointed out inthe description of that logic, A is ONE when a character has beencompletely shifted into the register 4. The A signal triggers theone-shot 107 through the Or gate 106. The output of the one-shot 107sets the BRI flip-flop 100 through the Or gate 108. The output atterminal 1 of the BRl flipop 100 then sets the BRZ dip-flop through theAnd gate 112. The other two inputs to the And gate 112, i.e. the outputsof the two inverters 111 and 114, are provided to ensure that the bufferwill not change its state while being interrogated. Thus, when Sel issent to interrogate the butter,

lli

the outputs of the two inverters 111 and 114 will both be ZEROpreventing the change of the BR2 flip-flop 101 from reset to set, andtherefore preventing the change of the BR signal from ZERO to ONE. Butwhen the buffer is not being interrogated and a character has beenreceived by the buffer register 4, the BRZ ip-fiop 101 will set. Uponthe next interrogation, the buffer will indicate that it has a characterready to be transferred to the computer (BR is ONE and BD is ZERO). Whenthe CMC13 receives this indication, Sel will remain at the ONE level,and CR will be a ONE thus transferring the character to the computerregister 5. The Sel-CR signal will also reset the BRZ iiip-op 101 andthe BR1 :dip-flop through the Or gate 102, thus establishing a not readycondition until the next character has been transferred to the bufferregister 4. When the last character of the message has been received andshifted into the computer register 5, the buffer will shift to neutral,and NS will become a ONE setting the BR1 ip-op 100 through the Or gate108. The BRR ip-op 101 then becomes set through the And gate 112indicating a ready condition (BR is ONE).

Consider next the transfer of data from the computer register 5 to theline l. Again, the buffer will be in the neutral mode until the CMCindicates that it is ready to send a character to the buder register 4.The CMC13 will first interrogate the buffer by sending Sel. The Selsignal will establish the interrogating pulse applied to the two Andgates 115 and 116. Since the buffer is in neutral, BR and BD will bothbe ONE. Sel will remain a ONE, and the CMC13 will send CR. Sel-CR willthen make the butter not ready (BR becomes ZERO) by resetting the BR2flip-dop 101 via the Or gate 102. The buffer will be shifted to transmitby the logic of FIG. 2. After a character has been transferred to thebuffer register from the computer register 5 and from the bufferregister 4 to the line 1, the BR2 flip-flop 101 will be set indicatingthat the buffer is ready to receive another character. The setting ofthe BRZ dip-flop 101 is accomplished by first setting the BR1 ip-ftop100 via the Or gate 108, the oneshot 107, the Or gate 106 and the Andgate 105. When a character has been shifted from the buffer register 4,the character time pulse, CT, will be ONE. TR is ONE because the bufferis in transmit. Therefore the output of the And gate will be a ONE andthe BRI flip-hop 100 will set causing the BR2 hip-flop 101 to set. Thecomputer will then send another character by causing Sel-CR to be a ONE.Sel-CR will reset the BRE flip-flop 101. When the last character of themessage has been sent, n0 more CR signals will be sent and the BRzHip-flop 101 will remain in its set condition.

The third input to the Or gate 108 is labeled ER. This signal isgenerated by the logic of FIG. 11. When ER is a ONE, it indicates thatthere is an error. For reasons to be described below, the ER signal isused to set the BR1 flip-Hop 100 which in turn sets the BRZ flip-flop101 indicating a ready state, BR is ONE.

FIG. l0 is a diagram of the logic used to detect certain errors. Thelogic comprises three And gates 90, 91, and 93 and an Or gate 92. Theoutputs of the two And gates 90 and 91 provide the Or gate 92 inputs.The output of the Or gate 92 is applied to one input of the And gate 93.The other input to the And gate 93 is a bit sample signal which isobtained from the counter. The bit sample signal is a ONE at the centerof a character bit. The output of the start ip-lop of the bulferregister is applied directly to the flip-flop 90 as is the data invertedor DATA from the line. The signals DATA and START are applied to theinputs of And gate 91. In this arrangement the output of gate 92 is theexclusive Or function of START and DATA, i.e. if START and DATA are notthe same, it is ONE. If they are the same, it is ZERO. In gate 93, thebit sample pulse is used to sample the output of gate 93. This isrequired to allow for delay between START and DATA. Since 13 the STARTand DATA signals should be the same while a character is beingtransferred to the line from the buffer, any difference in these twosignals represents an error and the signal E indicates the error bybeing a ONE. The error signal E is used in logic described below.

FIG. 11 is a diagram of the error detecting circuitry contained withinthe unit 12 of FIG. 1. This circuitry includes two Hip-flops 120 and 121labeled respectively ER1 and ERZ. The set input to the ER2 Hip-flop 121is taken from the output of the And gate 122 which receives the Sel-CRsignal and the condition at the output terminal 1 of the ERI flip-Hop120. The NS signal forms the reset input to the ER2 ip-fiop 121. The NSsignal also provides the input t'o the reset terminal R of the ERIflip-flop 120. The set input, terminal S, of the ER1 ipflop 129 is takenfrom the output of the Or gate 125 which receives three inputs. Thefirst input to the Or gate 125 is taken from the output of the And gate126 which receives three inputs, TR, DATA and the F signal developed atthe output terminal of the one-shot 106 in FIG. 9. The second input tothe Or gate 125 is taken from the output of the And gate 127 whichreceives three inputs, RC, CT, and D, D being supplied from the outputof the BRI flip-flop 100 in FIG. 9. The third input, labeled E, to theOr gate 125 is the output of t'he exclusive Or circuit of FIG. l0. Theoutput terminal O of the ERZ Hip-flop 121 provides the NER signal whichis used in conjunction with the logic of FIG. 9 i.e. it is an input tothe And gate 11S. The output terminal 1 of the ERZ flipdlop 121 is notused. The condition at output terminal 1 of the ERI flipflop 120 labeledER is supplied to the input of the And gate 130 which alos receives thesignal C developed by the logic of FIG. 9. The output terminal 1 of theERI flip-flop 120 provides the ER signal which is used in the logic ofFIG. 9. The output of the And gate 130 provides the error indicatingsignal, ERR which is supplied to the CMC13 when an error has beendetected.

The error detecting circuitry of FIG. 1 is responsive to certain errorswhich may occur when a message is being transmitted from the computer tothe line and to certain errors which may occur when the message is beingreceived from the line. First consider the case where data istransferred to the line. As soon as the buffer has transmitted onecomplete character of a Word to the line, the F output of the FIG. 9logic and the TR signal are both ONE. The condition of the line at thistime should be a ONE indicating the stop bit of the charat'cer. If thisis not the case, i.e. the condition of the line is a ZERO, there hasbeen an error and the output of the And gate 126 will be a ONE sinceDATA is a ONE. Such a situation may for example ocur when the line isbroken. The ONE output of the And gate 126 will set the ER1 flip-flop120 through the Or gate 125 indicating the error.

As noted above, the exclusive Or logic of FIG. performs an errordetecting function by comparing the data in the buffer register 4 bit bybit with the data on the line 1. When there is an error, the output ofthe FIG. 10 logic, E, will be ONE and it will set the ER1 flip-flop 120through the Or gate 125.

When the buffer is receiving data (RC is ONE), a complete character inthe buffer register 4 will cause the start and stop outputs of thebuffer register 4 to both be ONE. This condition will cause the BR1fiip-op 100 to set as explained above. The counter will indicate acharacter time (CT becomes ONE). If CT is ONE, but the character in theregister 4 does not contain the proper start and stop bits then the BR,ip-op 100 will not set and there is an error. The not set condition is`indicated by the D signal from the output of the BRl flip-flop 100. TheERI flip-flop 120 is set to indicate the error by the ONE condition atthe output of the And gate 127 caused by RC, CT and D all being ONEs.

The set condition of the ERI flip-Hop 120 will cause the output, ERR, ofthe And gate 130 to be a ONE when the C input to the And gate 130 is aONE. The C input is the interrogating pulse developed in the FIG. 9logic. Thus, when the CMC13 interrogates the And gate 130, if the ERlip-op 120 is set then ERR will be ONE indicating the error. The computermay be programmed to perform any desired operation when the error isindicated, for example it may be programmed to retransmit the messageover a different line. Once an error has been detected (ERI set) andindicated to the CMC (ERR is ONE) the buffer is placed in the not readycondition by changing the no error signal NER at the input to the Andgate 115 in FIG. 9 from a ONE to a ZERO. This change is accomplished bysetting the ERB ilipdlop 121 with the ER output signal from the ER1flip-Hop 120 through the And gate 122, when Sel-CR is ONE. The bufferwill then remain in the not ready state until it shifts to neutral. Theshift to neutral generates the NS pulse which resets the ER; flip-flop121 and clears the error indication.

In order to ensure that an error which has been detected will beindicated to the CMC13 as soon as possible, the ER output of the ER1dip-flop 120 is used to set a ready condition in the FIG. 9 logic. TheER signal is applied to the Or gate in FIG. 9 to set the BR1 flipdlopwhich in turn sets the BR flip-flop 101.

What is claimed is:

1. A buffer for controlling the transfer of data between a data handlingdevice and a transmission line comprising:

(a) a storing means,

(b) means for transferring data in either direction between said storingmeans and said device,

(c) means for transferring data in either direction between saidtransmission line and said storing means, and

(d) control means arranged and operated to place said transferring meansand said storing means in one of three modes including a rst modeenabling the transfer of data from said transmision line to said devicethrough said storing means, a second mode enabling the transfer of datafrom said device to said transmission line through said storing means,and a third mode enabling said transferring means and said storing meansto be switched to either said first or said second mode.

2. A buffer for controlling the transfer of data between a data handlingdevice and a transmission line, said device being of the type whichprovides control signals according to the status thereof, said buffercomprising:

(a) means for storing data,

(b) means for transferring data in either direction between said storingmeans and said device,

(c) means for transferring data in either direction betwen said storingmeans and said transmission line, an

(d) control means responsive to the data condition on said transmissionline and to said control signals from said device for establishing oneof three operating modes for said transferring means and said storingmeans including a first mode enabling the transfer of data from saiddevice to said storing means and from said storing means to said line, asecond mode enabling the transfer of data from said line to said storingmeans and from said storing means to said device, and a third modeenabling the transfer of data t-o said storing means from either saidline or said device, said control means establishing said first modewhen said device is ready to send data to said line while said storingmeans and said transferring means are in said third mode, establishingsaid second mode when data is received from said transmission line whilesaid storing means and said transferring means are in said third mode,and establishing said third mode in response to a predetermined datacondition on said line.

3. A buffer for controlling the transfer of data between 3,348,209 15 adata handling device and a transmission line, said device being of thetype arranged to produce control signals indxcatlve of the statusthereof, said buffer comprising:

from said device or from said transmission line to said device, (i)means responsive to the data condition on said (a) means for storingdata, (b) means for transferring data in either direction becording toand in response to the respective states of said first and second memoryelements. 5. A buffer for controlling the transfer of data betweentransmission line for placing only said first memory element in itssecond state when data is to be transtween said storing means and saiddevice, ferred from said transmission line to said device,

(c) means for transferring data in either direction be- (i) ineensresponsive io said eoniroi Signal from Said tween said storing means andsaid transmission line, oevioe for Placing 'said nrsl and second memoryele- (d) means responsive to the data on said transmission ments intheir second states when said device is ready line, to Said conti-oisignals from said devioo and to to send data to said transmission line,the condition of said buffer for enabling the transfer ik) ineensresponsive io ine 'sinies or Said iifSr and of data to said storingmeans from said transmission second l'rlernorv elel'nenis for operatingsaid nisiline and from said storing means to said device mentioned`nPPlying means t0 trnSfer data from whenever data is received over Saidlino land no data said transmission line to the input of said shiftregis being sont by said device; and for enabling the ister, foroperating said transferring means to transtransfer of data to saidstoring means from said fer data from said shift register to saiddevice, for device and from said storing means ro said transmisoperating said transferring means to inhibit the transsion line wheneversaid device is ready ro transfer fer of data from said device to saidshift register, for data to said storing means and no dara appears inoperating said second-mentioned applying means to said storing moans 2ninhibit the transfer of data from the output of said 4. Abuffer forcontrolling the transfer of data between slliri regisier io solo line,and for olie-riding Said a data handling device and a transmission line,said deeounier io advance sold srllii reglsier Wllen said iirsi vicebeing of the type which produces control signals memory element is inits second state and said secdetermined by the status thereof, saidbuffer comprising: ono inernorv element is in iis rirsi siare,

(n) means fOr Storing data, (l) means responsive to the states of saidfirst and (b) means for transferring data in either direction besecondmemory elements for operating said trans' tween said storing moans andsaid device, ferring means to transfer data from said device to (c)means for transferring data in either direction besaid slllii registerfor operniing Said second-men' tween said storing means and Saidtransmission line, ilorled applying means io aIlPlB ille ooipni of said(d) a first memory element having rsr and second go shift register tosaid transmission line, for operating states, said first-mentionedapplying means to inhibit the (e) a second memory @ien-ioni having first`md second transfer of data from said line to the input of said states,shift register, for operating said transferring means (f) meansresponsive to the data condition on said to inhibit the transfer of datafrom said shift register line foi placing said first and seoorrd memoryein 35 to said device, and for `operating said counter to adments intheir first states when a transfer of data has vallee solo sllliireglsier When said first n'lernory ele' been completed to saidtransmission line from said nient is in lis second stale and 'snidsecond memory device or from said transmission line to said device,elerlienl is in iis second siate- (g) means responsive to the datacondition on said 6- A boiler for ooniroiling the irnnsfei' o f darnbefanSmSSiOn line for placing said rst memory ele- #to tween a ndatahandlmg device and. a transmission line, ment in its second state whendata is to be transsolo devlee being or ille rYPe Wrileli ProdneesControl ferrod by said transferring moans from said trans ysignalsindicative of the status thereof, said buffer commission line to saiddevice through said storing Prislng means, (a) a shift register havingan input `and an output,

(h) means responsive to said control signals from said 4.3 (o) ineensfor advaneing said siiiri regisien ai illebii device for plaoing saidfirst and Second memory e1e rate of data transmitted over saidtransmissmn line, ments in their second states when data is to be trans-(o) a plurality or'iransfer giiies for enabling ille fransferred by saidtransferring means from said device rer or data in eliiler direenonbetween said Srnfr leg' to said transmission line through said storingmeans, isier and said deviee (i) means for operating said transferringmeans ac- (d) eoniloi means TESPOHSIV@ i0 data On Said transmission lineand to said control signals from said device for enabling the transferof data from said transmission line to the input of said shift registerand for operating said advancing means to advance said shift register atthe data bit rate when data is received from said transmission line,

a data handling device and a transmission line, said device producingcontrol signals determined by the status thereof, said buffercomprising:

(a) a shift register having an input and an output, (b) means forapplying data on said transmission line to the input of said shiftregister.

(e) means responsive to data on said transmission line, said controlsignals from said device and to the data in said shift register foroperating said advancing (c) means for applying the output of said shiftregister means io slop ille advance of solo slllii register and forenabling the transfer of data from said sh1ft to said transmission line,t t d d thm h d U f t s (d) means for transferring data in eitherdirection regis er o Sal .evlce ug Sal .aus er gae when a predeterminednumber of data blts have been between said shift register and saiddevice,

(e) a counter havin an out ut connected to said shift transferred tosald Shift reglster register for advangcing -saild shift register at thebit if) igeans repqnsivle U data lalq tranjmtlssin gute sai contro signas rom sai evxce an o e a a rate of data transmitted over saidtransmission line, in said Shift register for Operating said advancing(i) a orsi memory element having rst and Second means to advance saidshift register at the data bit 'sintesi rate after said predeterminednumber of data bits (g) a second memory element having first `and second7n have been transferred to said device SHCS, (g) means responsive tosaid control signals from said (h) means TCSPOnSiVC 'I0 the dataCondition 0n Said device and to data on said transmission line forentransmission line for placing said first and second abling thetransfer of a predetermined number of memory elements in their firststates when a transfer data bits from said device to said shift registerof data has `been completed to said transmission line 7K5 through saidtransfer gates, for operating said advancing means to advance said shiftregister at the data bit rate, and for applying the output of said shiftregister to said transmission line when said device is ready to transfera predetermined number of data bits to said transmission line and nodata is being received from said transmission line,

(h) means responsive to data on said transmission line, said controlsignals from said device and to the data in said shift register forindicating to said device whether said shift register contains or doesnot contain data and whether said shift register is being advanced.

7. A control means for a buffer, said buffer controlling the transfer ofdata in either direction between a data handling device and atransmission line, said device being of the type which produces controlsignals according to the status thereof, said control means comprising:

(a) first and second two state memory means,

(b) means for controlling the operation of said buffer in accordancewith the states of said first and second memory means,

(c) means responsive to data on said transmission line and to saidcontrol signals from said device for placing said first and secondmemory means in their first states when data is neither received fromsaid transmisison line nor ready to be transferred from said device,

(d) means responsive to data on said transmisison line and to saidcontrol signals from said device for placing only said first memorymeans in its second state when data is received from said transmissionline,

(e) means responsive to data on said transmission line and to saidcontrol signals from said device for placing said first and secondmemory means in their second states when said device is ready totransfer data to said transmission line.

8. A buffer for controlling the transfer of data between a data handlingdevice and transmission line where said device develops control signalsto indicate whether said device is ready to transmit or receive data,said buffer comprising:

(a) means for storing data,

(b) means for transferring data in either direction between said deviceand said storing means,

(c) means for transferring data in either direction between saidtransmission line and said storing means,

(d) a memory means having at least three states,

(e) control means responsive to the state of said memory means forcontrolling by the operation of said transferring means the transfer ofdata in either direction between said transmission line and said storingmeans and in either direction between said storing means and saiddevice; said control means enabling the transfer of data from saidtransmission line to said storing means and from said storing means tosaid device when said memory means is in its first state, for enablingthe transfer of data from said device to said storing means and fromsaid storing means to said transmission line when said memory means isin its second state, and for enabling the transfer of data to saidstoring means from either said line or said device when said memorymeans is in its third state.

9. A buffer as claimed in claim 8 and further including, meansresponsive to the data on said transmission line and to said controlsignals developed by said device for placing said memory means in itsrst state when data is received from said transmission line and saiddevice is not ready to transfer data to said transmission line, forplacing said memory means in its second state when said device is readyto transfer data to said transmission line, and for placing said memorymeans in its third state when no data is being received from saidtransmission line and said device is not ready to transfer data to saidtransmission line.

18 10. A buffer for controlling the transfer of data between a datahandling device and a transmission line, said device being of the typewhich produces control signals determined by the status thereof, saidbuffer comprising:

(a) a shift register having an input and an output,

(b) means for advancing said shift register at the 4bit rate of datatransmitted over said transmission line,

(c) a plurality of transfer gates for enabling the transfer of data ineither direction between said shift register and said device,

(d) means for transferring data in either direction between said shiftregister and said transmission line,

(e) a first memory means having two states,

(f) a second memory means having two states,

(g) a third memory means having two states,

(h) first control means responsive to the data on said transmission linefor placing said first and second memory means in their first stateswhen a predetermined data condition exists on said line,

(i) second control means responsive to the data condition on said lineand to said control signals from said device for placing only said firstmemory means in its second state when data is received from saidtransmission line and said device is not rea-dy to transfer data to saidtransmission line,

(j) third control means responsive to the data condition on said lineand to said control signals from said device for placing said first andsecond memory means in their second states when said device is ready totransfer data to said transmission line and no data is being receivedfrom said transmission line,

(k) means responsive to the change in said first memory means from itsrst to its second state for placing said third memory means in itssecond state when said change occurs,

(l) means responsive to said control signals from said device forplacing said third memory means in its second state when said device isready to transfer a predetermined number of data bits to said shiftregister,

(m) means responsive to the states of said first and second memoryelements, to the state of said shift register and to the operation ofsaid first control means for placing said third memory means in its rststate when said first control means places said first and second memorymeans in their first states, when a predetermined number of bits havebeen received by said shift register from said transmission line or whena predetermined number of bits which have been transferred to said shiftregister from said device have all been transferred to said transmissionline,

(n) means responsive to the state of said third memory means forindicating to said device the state of said third memory means,

(o) means responsive to the states of said first and second memory meansfor indicating to said device the states of said first and second memorymeans,

(p) means responsive to the states of said first and second memory meansfor enabling the transfer of a predetermined number of bits from saiddevice to said shift register through said plurality of transfcr gateswhen said rst memory means is in its first state or when said secondmemory means is in its second state, and for enabling the transfer of apredetermined number of bits of data from said transmission line to saidshift register when said second memory means is in its first state,

(q) means responsive to the states of said first and second memory meansfor enabling the transfer of a predetermined number of the bits in saidshift register to said device through said plurality of transfer gateswhen said first memory means is in its sec- 19 ond states and saidsecond memory means is in its first state,

(r) means responsive to the states of said first and second memory meansfor enabling the transfer of all the bits in said shift register to saidtransmission line when said rst memory means is in its second state andsaid second memory means is in its second state.

2D References Cited UNITED STATES PATENTS 7/1966 Brun et al S40-172.54/1967 Berezin B4G-172.5

ROBERT C. BAILEY, Primary Examiner,

R. B. ZACHE, Assistant Examiner.

1. A BUFFER FOR CONTROLLING THE TRANSFER OF DATA BETWEEN A DATA HANDLINGDEVICE AND A TRANSMISSION LINE COMPRISING: (A) A STORING MEANS, (B)MEANS FOR TRANSFERRING DATA IN EITHER DIRECTION BETWEEN SAID STORINGMEANS AND SAID DEVICE, (C) MEANS FOR TRANSFERRING DATA IN EITHERDIRECTION BETWEEN SAID TRANSMISSION LINE AND SAID STORING MEANS, AND (D)CONTROL MEANS ARRANGED AND OPERATED TO PLACE SAID TRANSFERRING MEANS ANDSAID STORING MEANS IN ONE OF THREE MODES INCLUDING A FIRST MODE ENABLINGTHE TRANSFER OF DATA FROM SAID TRANSMISSION LINE TO SAID DEVICE THROUGHSAID STORING MEANS, A SECOND MODE ENABLING THE TRANSFER OF DATA FROMSAID DEVICE TO SAID TRANSMISSION LINE THROUGH SAID STORING MEANS, AND ATHIRD MODE ENABLING SAID TRANSFERRING MEANS AND SAID STORING MEANS TO BESWITCHED TO EITHER SAID FIRST OR SAID SECOND MODE.